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FEATURES Low On Resistance (300 typ) Fast Switching Times t ON 250 ns max t OFF 250 ns max Low Power Dissipation (3.3 mW max) Fault and Overvoltage Protection (-40 V to +55 V) All Switches OFF with Power Supply OFF Analog Output of ON Channel Clamped Within Power Supplies If an Overvoltage Occurs Latch-Up Proof Construction Break Before Make Construction TTL and CMOS Compatible Inputs APPLICATIONS Existing Multiplexer Applications (Both Fault-Protected and Nonfault-Protected) New Designs Requiring Multiplexer Functions GENERAL DESCRIPTION
4/8 Channel Fault-Protected Analog Multiplexers ADG508F/ADG509F/ADG528F*
FUNCTIONAL BLOCK DIAGRAMS
ADG508F/ADG528F
S1 S1A DA S4A D S1B DB S8 ADG528F ONLY WR RS 1 OF 8 DECODER S4B 1 OF 4 DECODER
ADG509F
A0 A1 A2 EN
A0 A1 EN
2. ON channel turns off while fault exists. 3. Low RON. 4. Fast Switching Times. 5. Break-Before-Make Switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. Trench Isolation Eliminates Latch-up. A dielectric trench separates the p and n-channel MOSFETs thereby preventing latch-up.
ORDERING GUIDE
The ADG508F, ADG509F and ADG528F are CMOS analog multiplexers, the ADG508F and ADG528F comprising eight single channels and the ADG509F comprising four differential channels. These multiplexers provide fault protection. Using a series n-channel, p-channel, n-channel MOSFET structure, both device and signal source protection is provided in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from -40 V to +55 V. During fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. This protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. The ADG508F and ADG528F switch one of eight inputs to a common output as determined by the 3-bit binary address lines A0, A1 and A2. The ADG509F switches one of four differential inputs to a common differential output as determined by the 2bit binary address lines A0 and A1. The ADG528F has on-chip address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable the device. When disabled, all channels are switched OFF.
PRODUCT HIGHLIGHTS
Model1 ADG508FBN ADG508FBRN ADG508FBRW ADG508FTQ ADG509FBN ADG509FBRN ADG509FBRW ADG509FTQ ADG528FBN ADG528FBP ADG528FTQ
Temperature Range -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -55C to +125C
Package Option2 N-16 R-16N R-16W Q-16 N-16 R-16N R-16W Q-16 N-18 P-20A Q-18
1. Fault Protection. The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from -40 V to +55 V. When a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows.
*Patent Pending.
NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; RN = 0.15" Small Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADG508F/ADG509F/ADG528F-SPECIFICATIONS1
Dual Supply (V
DD =
+15 V
10%, VSS = -15 V
10%, GND = 0 V, unless otherwise noted)
T Version -55 C to +25 C +125 C VSS + 3 VDD - 1.5 400 450 0.6 5
Parameter ANALOG SWITCH Analog Signal Range RON
B Version -40 C to +25 C +85 C VSS + 3 VDD - 1.5 350 400
Units V min V max typ
Test Conditions/Comments
300
300
RON Drift RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage I D (OFF) ADG508F/ADG528F ADG509F Channel ON Leakage I D, IS (ON) ADG508F/ADG528F ADG509F FAULT Output Leakage Current (With Overvoltage) Input Leakage Current (With Overvoltage) Input Leakage Current (With Power Supplies OFF) DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tTRANSITION tOPEN tON (EN, WR) tOFF (EN, RS) tSETT, Settling Time 0.1% 0.01% ADG528F Only tW, Write Pulsewidth tS, Address, Enable Setup Time tH, Address, Enable Hold Time tRS, Reset Pulsewidth Charge Injection OFF Isolation CS (OFF) CD (OFF) ADG508F/ADG528F ADG509F POWER REQUIREMENTS IDD ISS
0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 60 30 60 30
-10 V < VS < +10 V, IS = 1 mA; VDD = +15 V 10%, VSS = -15 V 10% max -10 V < VS < +10 V, IS = 1 mA; VDD = +15 V 5%, VSS = -15 V 5% %/C typ VS = 0 V, IS = 1 mA % max VS = 0 V, IS = 1 mA nA typ nA max nA typ nA max nA max nA typ nA max nA max nA typ A max A typ A max A typ A max VD = 10 V, VS = Test Circuit 2 VD = 10 V, VS = Test Circuit 3 VS = VD = 10 V; Test Circuit 4 VS = 33 V, VD = 0 V, Test Circuit 3 VS = 25 V, VD = 10 V, Test Circuit 5 10 V; 10 V;
0.02 1 0.04 1 1 0.04 1 1 0.02 2 0.005 2 0.001 2
50 200 100 200 100
0.02 2 2 0.005 2 0.001 2 2.4 0.8 1 5 200 300 50 25 200 250 200 250
VS = 25 V, VD = VEN = A0, A1, A2 = 0 V Test Circuit 6
2.4 0.8 1 5 200 300 50 25 200 250 200 250
V min V max A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max s typ s typ ns min ns min ns min ns min pC typ dB typ dB min pF typ pF typ pF typ VIN = 0 or VDD
400 10 400 400 1 2.5
400 10 400 400 1 2.5
RL = 1 M, CL = 35 pF; VS1 = 10 V, VS8 = 10 V; Test Circuit 7 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 8 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 9 RL = 1 k, CL = 35 pF; VS = +5 V; Test Circuit 9 RL = 1 k, CL = 35 pF; VS = +5 V
100
120 100 10 100
100
200 100 10 100
4 68 50 5 50 25 0.1 0.1 0.2 0.1
4 68 50 5 50 25 0.1 0.1 0.2 0.1
VS = 0 V, RS = 0 , CL= 1 nF; Test Circuit 12 RL = 1 k, CL = 15 pF, f = 100 kHz; VS = 7 V rms; Test Circuit 13
mA max mA max
VIN = 0 V or 5 V
NOTES 1 Temperature ranges are as follows: B Version: -40C to +85C; T Version: -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. C
ADG508F/ADG509F/ADG528F
Table I. ADG508F Truth Table
A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH NONE 1 2 3 4 5 6 7 8 A1 X 0 0 1 1 A0 X 0 1 0 1
Table II. ADG509F Truth Table
EN 0 1 1 1 1 ON SWITCH PAIR NONE 1 2 3 4
X = Don't Care
X = Don't Care
Table III. ADG528F Truth Table
A2 X X X 0 0 0 0 1 1 1 1
A1 X X X 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1
EN X X 0 1 1 1 1 1 1 1 1
WR g X 0 0 0 0 0 0 0 0 0
RS 1 0 1 1 1 1 1 1 1 1 1
ON SWITCH Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 5 6 7 8
X = Don't Care
TIMING DIAGRAMS (ADG528F)
3V WR 0V 50% 50%
3V RS 0V 50% 50%
tW tS tH
3V A0, A1, A2 EN 0V 2V 0.8V
tRS tOFF (RS)
VO SWITCH OUTPUT 0V 0.8VO
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, tOFF (RS). Note: All digital input signals rise and fall times are measured from 10% to 90% of 3 V. tR = tF = 20 ns.
REV. C
-3-
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC
DIP/SOIC
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V VEN, VA Digital Input . . . . . . . - 0.3 V to VDD + 2 V or 20 mA, Whichever Occurs First VS, Analog Input Overvoltage with Power ON . . . . . VSS - 25 V to VDD + 40 V VS, Analog Input Overvoltage with Power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 V to +55 V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Cerdip Package JA, Thermal Impedance 16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W 18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300C Plastic Package JA, Thermal Impedance 16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117C 18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110C Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C SOIC Package JA, Thermal Impedance Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77C/W Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C PLCC Package JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
A0 EN VSS S1 S2 S3 S4 D
1 2 3 4 5 6 7 8
16 A1 15 A2 14 GND 13 VDD TOP VIEW (Not to Scale) 12 S5 11 S6 10 S7 9 S8
A0 EN VSS S1A S2A S3A S4A DA
1 2 3 4 5 6 7 8
16 A1 15 GND 14 VDD 13 S1B TOP VIEW (Not to Scale) 12 S2B 11 S3B 10 S4B 9 DB
ADG508F
ADG509F
ADG528F PIN CONFIGURATIONS
DIP
PLCC
WR
NC
A0
RS
WR A0 EN VSS S1 S2 S3 S4 D
1 2 3 4 5 6 7 8 9
18 RS 17 A1 16 A2 EN 4 VSS 5 S1 6 S2 7 S3 8
3
2
1
20 19 18 A2
A1 17 GND 16 VDD 15 S5 14 S6 S7
ADG528F
15 GND
ADG528F
TOP VIEW (Not to Scale)
TOP VIEW 14 VDD (Not to Scale) 13 S5 12 S6 11 S7 10 S8
9 S4
10 11 12 13 NC S8 D
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. C
ADG508F/ADG509F/ADG528F
TERMINOLOGY
Typical Performance Graphs
Most positive power supply potential. Most negative power supply potential. Ground (0 V) reference. Ohmic resistance between D and S. Change in RON when temperature changes by one degree Celsius.
RON -
2000 1750 1500 1250 1000 750 500 250 0 -15 VDD = +10V VSS = -10V VDD = +15V VSS = -15V -10 -5 0 5 VD (VS) - Volts 10 15 TA = +25 C
VDD VSS GND RON RON Drift RON Match IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) CD, CS (ON) CIN tON (EN)
VDD = +5V VSS = -5V
Difference between the RON of any two channels. Source leakage current when the switch is off. Drain leakage current when the switch is off. Channel leakage current when the switch is on. Analog voltage on terminals D, S. Channel input capacitance for "OFF" condition. Channel output capacitance for "OFF" condition. "ON" switch capacitance. Digital input capacitance. Delay time between the 50% and 90% points of the digital input and switch "ON" condition. Delay time between the 50% and 90% points of the digital input and switch "OFF" condition. Delay time between the 50% and 90% points of the digital inputs and the switch "ON" condition when switching from one address state to another. "OFF" time measured between 80% points of both switches when switching from one address state to another. Maximum input voltage for Logic "0". Minimum input voltage for Logic "1". Input current of the digital input. A measure of unwanted signal coupling through an "OFF" channel. A measure of the glitch impulse transferred from the digital input to the analog output during switching. Positive supply current. Negative supply current.
Figure 3. On Resistance as a Function of VD (VS)
1m 100 VDD = 0V VSS = 0V VD = 0V
IS - INPUT LEAKAGE - A
10 1 100n 10n OPERATING RANGE 1n 100p 10p
tOFF (EN)
tTRANSITION
1p -50 -40 -30 -20 -10 0 10 20 30 VIN - INPUT VOLTAGE - Volts
40
50
60
tOPEN
Figure 4. Input Leakage Current as a Function of VS (Power Supplies OFF) During Overvoltage Conditions
VINL VINH IINL (IINH) Off Isolation Charge Injection
1m 100
I D - INPUT LEAKAGE - A
10 1
VDD = +15V VSS = -15V VD = 0V
100n 10n OPERATING RANGE 1n
IDD ISS
100p 10p 1p -50 -40 -30 -20 -10 0 10 20 30 VIN - INPUT VOLTAGE - Volts 40 50 60
Figure 5. Output Leakage Current as a Function of VS (Power Supplies ON) During Overvoltage Conditions
REV. C
-5-
ADG508F/ADG509F/ADG528F
2000 1750
100
LEAKAGE CURRENTS - nA
1500 1250
VDD = +15V VSS = -15V
10
VDD = +15V VSS = -15V VD = +10V VS = -10V
ID (OFF)
RON -
1000 750 500 250 +25 C 0 -15 -10 -5 0 5 VD (VS) - Volts 10 15 +85 C +125 C
1 IS (OFF) 0.1
ID (ON)
0.01 25
35
45
55
85 95 65 75 TEMPERATURE - C
105
115
125
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures
Figure 9. Leakage Currents as a Function of Temperature
1m 100 VDD = +15V VSS = -15V VD = 0V
260 VIN = +2V 240 220 200
IS - INPUT LEAKAGE - A
10 1
tON (EN)
t - ns
OPERATING RANGE
100n 10n 1n 100p 10p 1p -50 -40
180 160 140
tTRANSITION
tOFF (EN)
120 100 10
-30 -20 -10 0 10 20 30 VIN - INPUT VOLTAGE - Volts
40
50
60
11
12 13 VSUPPLY - Volts
14
15
Figure 7. Input Leakage Current as a Function of VS (Power Supplies ON) During Overvoltage Conditions
Figure 10. Switching Time vs. Power Supply
0.3 VDD = +15V VSS = -15V TA = +25 C IS (OFF) 0.1 ID (OFF)
280 260 240 220 VDD = +15V VSS = -15V VIN = +5V
LEAKAGE CURRENTS - nA
0.2
tON (EN)
t - ns
200 180 160 140 120
tTRANSITION
0.0 ID (ON) -0.1
tOFF (EN)
45 65 85 TEMPERATURE - C 105 125
-0.2 -14
-10
-6
-2 2 VS, VD - Volts
6
10
14
100 25
Figure 8. Leakage Currents as a Function of VD (VS)
Figure 11. Switching Time vs. Temperature
-6-
REV. C
ADG508F/ADG509F/ADG528F
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable of withstanding overvoltages from -40 V to +55 V, irrespective of whether the power supplies are present or not. Each channel of the multiplexer consists of an n-channel MOSFET, a pchannel MOSFET and an n-channel MOSFET, connected in series. When the analog input exceeds the power supplies, one of the MOSFETs will switch off, limiting the current to submicroamp levels, thereby preventing the overvoltage from damaging any circuitry following the multiplexer. Figure 12 illustrates the channel architecture that enables these multiplexers to withstand continuous overvoltages. When an analog input of VSS + 3 V to VDD - 1.5 V is applied to the ADG508F/ADG509F/ADG528F, the multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 400 maximum. However, when an overvoltage is applied to the device, one of the three MOSFETs will turn off. Figures 12 to 15 show the conditions of the three MOSFETs for the various overvoltage situations. When the analog input applied to an ON channel approaches the positive power supply line, the n-channel MOSFET turns OFF since the voltage on the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel MOSFET will turn off since the analog input is more negative than the difference between VSS and the p-channel threshold voltage (VTP). Since VTN is nominally 1.5 V and VTP is typically 3 V, the analog input range to the multiplexer is limited to -12 V to +13.5 V when a 15 V power supply is used. When the power supplies are present but the channel is off, again either the p-channel MOSFET or one of the n-channel MOSFETs will turn off when an overvoltage occurs. Finally, when the power supplies are off, the gate of each MOSFET will be at ground. A negative overvoltage switches on the first n-channel MOSFET but the bias produced by the overvoltage causes the p-channel MOSFET to remain turned off. With a positive overvoltage, the first MOSFET in the series will remain off since the gate to source voltage applied to this MOSFET is negative. During fault conditions, the leakage current into and out of the ADG508F/ADG509F/ADG528F is limited to a few microamps. This protects the multiplexer and succeeding circuitry from over stresses as well as protecting the signal sources which drive the multiplexer. Also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue to operate normally.
+55V OVERVOLTAGE n-CHANNEL MOSFET IS OFF Q1 Q2 Q3
+55V OVERVOLTAGE n-CHANNEL MOSFET IS OFF VDD
Q1
Q2
Q3
VSS
Figure 12. +55 V Overvoltage Input to the ON Channel
Figure 14. +55 V Overvoltage with Power OFF
-40V OVERVOLTAGE n-CHANNEL MOSFET IS ON VSS
Q1
Q2
Q3
-40V OVERVOLTAGE n-CHANNEL MOSFET IS ON
Q1
Q2
Q3
VDD
p-CHANNEL MOSFET IS OFF
p-CHANNEL MOSFET IS OFF
Figure 13. -40 V Overvoltage on an OFF Channel with Multiplexer Power ON
Figure 15. -40 V Overvoltage with Power OFF
REV. C
-7-
ADG508F/ADG509F/ADG528F Test Circuits
IDS
VDD VSS VSS D VDD ID (ON) A VD EN +2.4V
V1
S1 S2 S8
S VS
D
VS
RON = V1 /IDS
Test Circuit 4. ID (ON) Test Circuit 1. On Resistance
VDD VSS VSS
VDD
VSS
A
VDD S1 S2 S8
IS (OFF) A
VDD S1 S2
VSS
D VD
D
EN VS
+0.8V
VS
S8 EN VD +0.8V
Test Circuit 5. Input Leakage Current (with Overvoltage) Test Circuit 2. IS (OFF)
0V VDD 0V A2 A1
VDD S1 ID (OFF) S2 S8 EN VS +0.8V D A VD VSS
0V VSS S1 A VS
VDD
VSS
ADG528F*
S8 D WR
A0 EN RS GND
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 3. ID (OFF)
Test Circuit 6. Input Leakage Current (with Power Supplies OFF)
VDD
VSS 3V VSS S1 S2-S7 S8 VS8 VOUT RL 1M CL 35pF 90% VS1
VDD A2 VIN 50 A1 A0 +2.4V EN RS GND
ADDRESS DRIVE (VIN)
50%
50%
ADG528F*
D WR
VOUT
90%
* SIMILAR CONNECTION FOR ADG508F/ADG509F
tTRANSITION
tTRANSITION
Test Circuit 7. Switching Time of Multiplexer, tTRANSITION
-8-
REV. C
ADG508F/ADG509F/ADG528F
VDD VSS 3V VDD A2 VIN 50 A1 A0 RS +2.4V EN GND WR VSS S1 S2-S7 VS
ADDRESS DRIVE (VIN)
ADG528F*
S8 D RL 1k CL 35pF VOUT 80%
VOUT
80%
tOPEN
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 8. Break-Before-Make Delay, tOPEN
VDD
VSS 3V
VDD A2 A1 A0 +2.4V RS EN VIN 50 GND
VSS S1 S2-S8 VS
ENABLE DRIVE (VIN)
0V
50%
50%
ADG528F*
D WR RL 1k CL 35pF VO VOUT 0.9VO
tOFF (EN)
0.9VO
OUTPUT
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 9. Enable Delay, tON (EN), tOFF (EN)
VDD VDD A2 A1 A0 +2.4V EN RS WR VRS VWR GND
VSS 3V VSS S1 S2-S8 VS 0V
WR
50%
ADG528F
VO D RL 1k CL 35pF VOUT
tON (WR)
OUTPUT
0.2VO 0V
Test Circuit 10. Write Turn-On Time, tON (WR)
REV. C
-9-
ADG508F/ADG509F/ADG528F
VDD VDD A2 A1 A0 +2.4V EN RS VIN GND WR D RL 1k CL 35pF VOUT VSS 3V VSS S1 S2-S8 VS 0V
RS
50%
50%
ADG528F
VO
tRS tOFF (RS)
0.8VO
SWITCH OUTPUT
0V
Test Circuit 11. Reset Turn-Off Time, tOFF (RS)
VDD
VSS 3V +2.4V
VDD A2 A1 RS VS VIN A0 S EN GND
VSS RS
ADG528F*
D CL 1nF WR VOUT
LOGIC INPUT (VIN)
0V
VOUT
Q INJ = CL x VOUT
VOUT
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 12. Charge Injection
VDD VDD A2 A1 A0 +2.4V RS EN GND WR VSS D RL 1k VOUT
S1 S8 VIN
ADG528F*
VSS * SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 13. OFF Isolation
-10-
REV. C
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic (N-16)
0.840 (21.34) 0.745 (18.92)
16 1 9 8
16-Lead Cerdip (Q-16)
0.005 (0.13) MIN
16
0.080 (2.03) MAX
9
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC
0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.310 (7.87) 0.220 (5.59)
1 8
PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.070 (1.77) SEATING 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.100 (2.54) BSC
0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76)
15 0
0.015 (0.38) 0.008 (0.20)
16-Lead SOIC (R-16N) (Narrow Body)
16-Lead SOIC (R-16W) (Wide Body)
0.4133 (10.50) 0.3977 (10.00)
16 9
0.3937 (10.00) 0.3859 (9.80)
16 1 9 8
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
1
8
PIN 1
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
0.0118 (0.30) 0.0040 (0.10)
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
REV. C
-11-
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Plastic (N-18)
0.925 (23.49) 0.845 (21.47)
18 1 10 9
18-Lead Cerdip (Q-18)
0.005 (0.13) MIN
18
0.098 (2.49) MAX
10
0.280 (7.11) 0.240 (6.10)
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.310 (7.87) 0.220 (5.59)
1 9
PIN 1 0.960 (24.38) MAX 0.200 (5.08) MAX 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE
0.320 (8.13) 0.290 (7.37)
0.015 (0.381) 0.008 (0.204)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
15 0
0.015 (0.38) 0.008 (0.20)
20-Lead PLCC (P-20A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
3 4
19 18 PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 8 9 14 13
0.050 (1.27) BSC
0.020 (0.50) R
0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78)
-12-
REV. C
PRINTED IN U.S.A.
C1979c-0-8/98

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